Communication transmitters traditionally employ a phase locked loop (PLL) for frequency synthesis of a communication carrier signal modulated with transmission data. The PLL allows the carrier signal frequency to be precisely controlled and, accordingly, permits the data on which the carrier signal modulation is based to be reliably transmitted at a stable, known frequency. A conventional PLL frequency synthesizer is shown in FIG. 1 and includes a voltage controlled oscillator (VCO) 100 that produces a VCO output signal 102 at a desired frequency based on a VCO frequency control signal 104. VCO frequency control signal 104 is generated by a feedback loop 106. VCO output signal 102 is coupled through feedback loop 106 to a phase-frequency detector 108 which compares the phase (or frequency) of VCO output signal 102 (or multiple thereof as described below) to that of a fixed-frequency reference signal 110. Phase-frequency detector 108 generates an error signal 112 corresponding to a phase (or frequency) difference between VCO output signal 102 and fixed-frequency reference signal 110. A charge pump 114 converts error signal 112 from phase-frequency detector 108 into a charge pump output signal 116. Charge pump output signal 116 is smoothed by a low pass loop filter 118 to generate VCO control signal 104. VCO control signal 104 is then applied to VCO 100 such that, in its steady state, the phase (or frequency) of VCO output signal 102 matches that of fixed-frequency reference signal 110.
Typically, a frequency divider 120 is included in PLL feedback loop 106 to divide the frequency of VCO output signal 102 to a frequency that is a multiple of that of fixed-frequency reference signal 110. Frequency divider 120 generates a divided frequency output signal 122 that is compared by phase-frequency detector 108 to fixed-frequency reference signal 110. The frequency of a carrier signal produced by VCO 100 is constantly controlled such that it is phase locked to a multiple of that of fixed-frequency reference signal 110. For example, if frequency divider 120 divides by integers only, the smallest increment (i.e., step size) in the frequency of VCO output signal 102 is equal to the frequency of fixed-frequency reference signal 110.
To increase the VCO output frequency resolution, frequency divider 120 is typically implemented as a fractional divider. A fractional divider fractionally divides an input signal. In one example, a control circuit controls an integer component (N) and a fractional component (F) by which the frequency of VCO output signal 102 is divided. Different techniques can be used to implement fractional N division. In one technique, division by (N)(F) is achieved by averaging the divisor such that the output frequency is divided by (N) for (F) portion of a duty cycle and divided by (N+1) for (1−F) portion of the duty cycle. Switching between divisors in a fixed, periodic pattern, however, results in fractional spurs—i.e., undesirable phase jitter or phase noise near the carrier frequency.
A general technique to reduce fractional spurs is to cascade multiple stages of first or second order sigma delta modulators and supply an output of each stage to digital cancellation logic as described in “Delta Sigma Data Converters Theory, Design, and Simulation (Steven R. Norsworthy et. Al), IEEE Press (1997).
One particular feature of sigma delta modulated PLLs is that a sigma delta modulator introduces quantization noise at a high frequency that is proportional to the step size of the dividing ratio. The dividing ratio is the ratio of the VCO output frequency and the output frequency of the divider. For example, if the step size is 2 (i.e., the dividing ratio of the first divider is N/N+2, such that the overall dividing ratio is even and can be increased in unit steps of 2), the quantization noise will be 6 dB higher compared to the case in which the step size is 1 (i.e., the dividing ratio of the first divider is N/N+1, such that the overall dividing ratio can be even and increased in unit steps of 1).